The present invention relates to a memory device with an improved sense amplifier.
Semiconductor IC memories are widely used. Typical examples of this type of memories are a read only memory (ROM) and a random access memory (RAM). The readout of stored data from the ROM or the RAM is performed by a sense amplifier. There is yet room for improvement on the readout speed of the stored data by a prior art sense amplifier.
FIG. 1 shows a configuration of a general semiconductor read only memory (ROM). Illustrated in the figure are a column decoder 1, column lines (data lines) 2, column selecting MOS transistors 3, a row decoder 4, row lines (word lines) 5, MOS transistors 6 forming memory cells each of which is driven by the corresponding line 5, a load MOS transistor 7 for charging the lines 2, and a sense amplifier 8 with an output buffer. The transistors 3 and 6 are of the enhancement type. The transistor 7 is of the depletion type.
The operation of the ROM will be described. First a given column selecting transistor 3 is driven by the decoder 1 to select a corresponding data line 2 connected with the transistor 3. Second, a given word line 5 is selected by the row decoder 4. A memory cell transistor 6 provided at a cross point of the selected lines 2 and 5 is driven by the selected line 5. The selected line 2 and a sensing point S are discharged (an ON state of the transistor 6) or charged (an OFF state of the transistor 6) in accordance with the stored data (represented by ON or OFF state) of the selected transistor 6. The charging operation is performed by a power supply potential E through the load transistor 7. The stored data of the selected transistor 6 corresponds to a potential of the selected line 2. The sense amplifier 8 connected to the sensing point S senses the potential of the selected line 2. The stored data sensed by the amplifier 8 is read out through the output buffer in the amplifier 8.
The stored data of the memory cell transistor 6 is determined depending on whether or not a drain (or a source) of the transistor 6 is connected to the data line 2. Assume now that the decoders 1 and 4 select a specific transistor 6 with its drain connected to the data line 2. On this assumption, the charge stored in the capacitances of the selected line 2 and the sensing point S are discharged by way of a drain-source path of the selected transistor 6. When a selected transistor 6 with the drain unconnected to the data line 2 (in a cutoff state) is selected, the selected line 2 and the sensing point S are charged by the potential E via the transistor 7. The sense amplifier 8 detects either of two states of the data line 2, i.e., charge or discharged state of the data line 2, and outputs either logic 0 or logic 1, whichever is the stored data.
FIG. 2 shows a simple equivalent circuit for illustrating the charge and discharge of either data line 2 shown in FIG. 1. In FIG. 2, resistance R7 represents an internal resistance of the load transistor 7. Resistance R6 is representative of a conduction resistance of the memory cell transistor 6. The symbols R6 and R7 are also used to indicate equivalent resistors for providing the corresponding resistances. Switches S3 and S6 represent ON and OFF functions of the transistors 3 and 6, respectively. A capacitance C indicates a total capacitance of the data line 2 and the sensing point S. In this example, the conduction resistance of the transistor 3 is much smaller than the resistance R7 and therefore is neglected. Alternately, it may be considered that the resistance R7 includes the conduction resistance of the transistor 3.
FIG. 3 shows time varying curves of a charged voltage VC or a sense potential VS of the capacitance C shown in FIG. 2. Before time t10, the switch S3 is ON, while the switch S6 is OFF, and the line 2 is charged up to the power supply potential E. At time t10, when a memory cell transistor 6 having the stored data of logic 0 is selected by the row decoder 4, the switch S6 is ON. Then, the line 2 is discharged to a dividend potential {R6/(R6+R7)} E, or a minimum potential Ed, by the resistances R6 and R7. When, at a time t20, a memory cell transistor with its stored data of logic 1 is selected, the switch S6 is OFF. Then, the line 2 is charged up to the maximum potential E.
A threshold level VTH for distinguishing logic 0 from logic 1 and vice versa is set midway between the potentials E and Ed. The stored data "logic 0" is sensed when the sense potential VS is less than the level VTH. The stored data "logic 1" is sensed when the sense potential VS is more than the level VTH. Accordingly, the read out time of the logic 0 is TL1, and the read out time of the logic 1 is TH1.
In FIG. 3, the resistance R7 of a broken curve as plotted is larger than that of a solid curve. As the resistance R7 is larger, the minimum potential Ed is lower and the read out time TL2 of the logic 0 is shorter (TL2&lt;TL1). When the resistance R7 becomes larger, however, a time constant C.times.R7 of the resistance R7 and the capacitance C is larger, so that the read out time TH2 of the logic 1 becomes longer (TH2&gt;TH1). Conversely, when the resistance R7 is made small in order to shorten the read out time TH2, the read out time TL2 is elongated. If both the resistances R6 and R7 are made small, both the read out times TL and TH can be shorter, but there is limit in how small the resistance can be made.
Generally, in a semiconductor memory device, particularly a ROM, a transistor with the shortest possible channel length and width is used for each memory cell in order to make the chip size small as possible. To reduce the resistance R6 as mentioned above results in enlarging the channel width the transistor 6. Therefore, the memory size and hence the chip size are also made large. This is the reason for the restriction in reducing the size of the resistance R6.
As a result of the progress of the integrating technology in microelectronics, the transistor size is further reduced while the memory capacity of the semiconductor memory is increased. Accordingly, the number of transistors connected to one data line 2 is correspondingly increased, resulting in the increase of a capacity of the data line 2. Consequently, the ratio of charge/discharge time of the data line 2 to the total read out time is increased (address data inputted to the memory data is read out from the output buffer 8). In the case of FIG. 2, this is equivalent to the increase of the capacitance C. Accordingly, it is impossible to to make both the read out times TL and TH small, and therefore, the selection of the read out times TL and TH must be a compromise between both the times.
The read out times TL and TH can be changed by adjusting the threshold level VTH. Even this method involves a conflicting interrelation between the shortenings of the time TL and the time TH. When the level VTH is set high, the time TL can be made short, but the time TH is long. Conversely, when the level VTH is set low, the time TH can be made short, though the time TL is long. Therefore, it is impossible to shorten both the read out times TL and TH, whatever threshold VTH is selected.